| Double-data-rate architecture; two data transfers per clock cycle |
| Bi-directional data strobe (DQS) |
| Differential clock inputs (CK and /CK) |
| DLL aligns DQ and DQS transition with CK transition |
| Auto & self refresh capability |
| Single 2.5V ±0.2V power supply |
| Programmable Read latency 2, 2.5 (clock) |
| Programmable Burst length (2, 4, 8) |
| Programmable Burst type (Sequential & Interleave) |
| Edge aligned data output, center aligned data input |
| Serial presence detect with EEPROM |
| PCB : Height (1,181 mil) |