|
Performance range
|
|
Power supply: VDD1.8V±0.1V Power supply
|
|
Bi-directional data strobe (DQS-DQS#)
|
|
Differential clock inputs (CK and CK#)
|
|
DLL aligns DQ and DQS transition with CK transition
|
|
Auto & self refresh capability (8192 Cycles / 64ms)
|
|
Double-data-rate architecture; two data transfers per clock cycle
|
|
Programmable Read latency : 3, 4 and 5 (clock)
|
|
Programmable Additive Latency: 0, 1, 2, 3 and 4
|
|
Programmable Burst length：4 or 8
|
|
Programmable Burst type (Sequential & Interleave)
|
|
Edge aligned data output, center aligned data input
|
|
Serial presence detect with EEPROM
|