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Double-data-rate architecture; two data transfers per clock cycle |
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Bi-directional data strobe (DQS) |
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Differential clock inputs (CK and /CK) |
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DLL aligns DQ and DQS transition with CK transition |
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Auto & self refresh capability |
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Single 2.5V ±0.2V power supply |
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Programmable Read latency 2, 2.5 (clock) |
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Programmable Burst length (2, 4, 8) |
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Programmable Burst type (Sequential & Interleave) |
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Edge aligned data output, center aligned data input |
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Serial presence detect with EEPROM |
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PCB : Height (1,181 mil ) |